[Ground-station] RTL Components for DVB-S2 - update from Suoto

[Michelle Thompson]

Suoto writes:

"I've set up a basic CI via GitHub actions on
https://github.com/phase4ground/dvb_fpga using a Docker container based on
Ubuntu 19.04, with GNU Radio 3.7.13.4, ModelSim Intel Starter 10.6d and
VUnit.

It's taking ~30 min to run 144 sims for a total of 553 tests, not that bad
for CI, but this is only testing 2 components from the DVB spec (BCH
encoder and bit interleaver) and a couple of other building blocks (AXI
file reader, AXI file compare, AXI stream delay).

Bit interleaver is mostly OK, just have to work out how to handle some
corner cases that are a bit trickier than I thought

phase4ground/dvb_fpga
RTL implementation of components for DVB-S2
Language
VHDL
Last updated
8 minutes ago
<https://github.com/phase4ground/dvb_fpga|phase4ground/dvb_fpga>

The cases where the bit interleaver fail are detected on the CI, that's why
the run is failing at the moment by the way"

Thank you to Suoto! Please review and if you see a place you can help,
pitch in.

-Michelle W5NYV
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