[Ground-station] Polyphase Filterbank from Theseus Cores update

[Michelle Thompson]

Efforts to solve the "timeout on channel 0" problem with the channelizer
continued today. Here's the ups and downs.

There's been quite a bit of work done over the past several weeks on the
cores. There has also been an update made to the UHD from Ettus.

However, when trying to test all these updates in our lab, they didn't
"take" as easily as expected! The image builder refused to build, and there
were some unrelated problems getting the Xilinx license re-started.

Lots of excitement and plenty of typing but we had not yet gotten to the
point where we could test the updated filterbank on the air.

After figuring out which fork was what with lots of help from EJ Kreiner
the updated code was running again in GNU Radio on a USRP X310.

But! The plot thickened again! It still timed out. Hm!

A git status revealed what was going on backstage. Heads were detached and
commits we assumed were part of UHD had not yet made it in.

After some more git-fu and a rebuild of the image with the correct
environment and changes, we loaded up the image and tried the flowgraph
again.

Timeouts now occur even faster! Not exactly the direction we were going
for, but it's probably something simple. Testing on their end has given
much better results.

All of this leads one to think about how we can try and reduce the
difficulty of the work. Stand-alone FPGA work is hard enough. But, what
we're up to is not just FPGA, but FPGA images in the context of a DSP
framework for SDR. So what should future tools and work look like?

There are some really neat ideas from EJ Kreiner about how to make Theseus
Cores easier to use. I hope they come about! Maybe he can describe them
here.

In the short term, we will very soon need an updated license for Xilinx
Vivado in order to continue R&D with RFNoC. I've asked Xilinx for help.
Failing that, we may have to hold a fundraiser to buy a license.

Another parallel effort is to campaign for a non-commercial non-academic
inexpensive "home" license for Vivado, in the same pattern as the one from
MATLAB ($150 for home use).

It would be ideal to have a completely open tool chain for FPGA/SDR work.
RFNoC uses Vivado, so that is why we have pursued licenses and use Vivado
almost exclusively.

There are several active free and open source FPGA tool chain efforts. It
isn't clear to me how far apart RFNoC and the FOSS tools are today, but at
least one tool chain targets Xilinx 7.

So, plenty going on.

Thoughts, comments, questions, ideas? Let us know!

Being able to use our FPGAs on SDRs to their fullest extent is quite the
superpower. Free and open source Theseus Cores directly addresses a
long-term goal of the GNU Radio community. The work done by Theseus Cores
is greatly appreciated.

If you haven't had a chance to check them out, then follow this link:
https://gitlab.com/theseus-cores/theseus-cores

-Michelle W5NYV
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