[Ground-station] Baseband => decimation - questions

[Scotty Cowling]

Hi David,

The rate from the ADC to the FPGA can be mitigated somewhat by wider 
parallel interfaces, but the method these days seems to be toward 
higher-speed serial interfaces.

The lower-cost FPGAs typically have some number of LVDS (differential 
pairs) that can run at anywhere from a few hundred up to 1Gbps. They 
typically use 8b/10b encoding, so you get 8 bits and a recovered clock 
out of the LVDS block in the FPGA at 10% of the encoded bit rate (like 
100M Byte/sec).

The fancier (and higher speed) ADCs use high speed transceivers to send 
the data at up to 3.12Gb/s (JESD204A) or 12Gb/s (JESD204B) speeds. 
Transferring data at these speeds requires an FPGA with high-speed 
transceivers, which are usually on the more expensive end of the 
spectrum (especially if you want to run at 12Gb/s). The other thing to 
beware of is that the higher-end FPGAs usually aren't supported by the 
free version of the tools. Altera/Intel Cyclone V GX and SX families 
have transceivers that run up to 3.125Gb/s, while the Cyclone V GT and 
ST variants have transceivers that run up to 6.144Gb/s. All Cyclone V 
parts are covered by the free tools. The "S" versions in the series (SX 
and ST) are SoC parts that contain on-board ARM CPUs (either single or 
dual core).

So we get boxed in by the required FPGA performance and the (usually 
large) cost of the full version of the tools. It would be great if you 
can find an ADC that is both affordable and that we can interface to a 
reasonably priced FPGA. There are some amazing parts made today, but it 
is a hard selection process with so many variables to consider.

73,
Scotty WA2DFI

On 2019-02-02 14:51, David Vieira wrote:
> Scott -
> I like the idea of a single Mixer and no phase shifter to create I/Q 
> in the RF/analog world.
> That would help a lot with discrete, high performance designs.
>
> As for the core question - what is the rate from ADC to FPGA --- that 
> seems both flexible yet with out a clear cut answer.
> Lots of good discussion to box in the trade-offs, though.
>
> I'll try and look at discrete ADC options that could handle the range 
> of 144 or even 900 MHz, with at least nyquist sampling.
>
> regards,
>
> David, KI6CLA
> dpv at ieee.org
>
>
> On Saturday, February 2, 2019, 1:13:15 PM PST, Scotty Cowling via 
> Ground-Station <ground-station at lists.openresearch.institute> wrote:
>
>
> This is a great discussion, sorry I have arrived so late in the thread.
>
> Since I am a FPGA and a hardware guy, my comments are hardware-centric.
> Probably makes me odd man out, but here goes...
>
> I greatly favor a single ADC at a higher rate (than dual ADCs clocked in
> phase or quadrature). The I and Q samples can be generated
> mathematically inside the FPGA without the analog mismatch problems
> associated with trying to build two identical copies of analog and ADC
> hardware. The quadrature mixers are implemented in digital hardware to
> whatever precision the hardware allows. Of course, there is a price to
> be paid. The ADC has to run twice as fast, and wider NCOs and
> multipliers use FPGA fabric and require fasted logic. Both cost $$
>
> While the AD9361 is a fantastic part, we pay for all the features
> whether we use them or not. Mixers and oscillators all add noise,
> whether they are all integrated inside one chip or spread out. System
> engineering is in order.
>
> As Zach said, every decimation by 4 increases dynamic range by
> approximately 1 bit. So we should sample as fast as possible, and
> decimate in the digital domain. Except that ADC width and speed cost
> money, and the FGPA's ability to consume and process data is limited in
> speed. So we want to pick ADC width, clock speed and FPGA based on the
> knee of the price-performance curve. This "knee" is always moving, which
> is why today's hardware is better than yesterday's (well, usually).
>
> My guess is that the practical, affordable ADC performance today is at
> ~125Msps and either 14 or 16 bits. Interestingly, affordable FPGAs can
> handle 150MHZ to 200MHz at their inputs and outputs without too much
> problem. Go much faster, and you get really expensive really fast. The
> same with resources. I am most familiar with Altera/Intel FPGAs, so
> someone with Xilinx experience can add to this. The best cost per logic
> element seems to be either the MAX10M50 (50K LEs) or the Cyclone 5 E
> (logic only series). The C5E goes up to 300K LEs (which is a lot, and
> costs appropriately). If we want a dual-core ARM hard processor
> (per-configured in silicon, using zero LEs), the Cyclone 5 SE at 110K
> LEs is probably the best bet.
>
> So where does this leave us for P4G hardware? Some kind of down
> conversion at the antenna is pretty obvious. Is it better to use an off
> the shelf LNB to a higher frequency (e.g., 900MHz) and then down-convert
> to base band at the SDR receiver front end? Or is it better to use a
> custom LNB and down convert directly to a base band frequency (say
> 30MHz) that can be directly sampled?
>
> A third option would be to build a VHF or UHF direct-sampling  SDR (at
> 900MHz, to use the above example), but I think that would be too 
> expensive.
>
> 73,
> Scotty WA2DFI
>
>
>
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