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Hi David,<br>
<br>
The rate from the ADC to the FPGA can be mitigated somewhat by wider
parallel interfaces, but the method these days seems to be toward
higher-speed serial interfaces.<br>
<br>
The lower-cost FPGAs typically have some number of LVDS
(differential pairs) that can run at anywhere from a few hundred up
to 1Gbps. They typically use 8b/10b encoding, so you get 8 bits and
a recovered clock out of the LVDS block in the FPGA at 10% of the
encoded bit rate (like 100M Byte/sec).<br>
<br>
The fancier (and higher speed) ADCs use high speed transceivers to
send the data at up to 3.12Gb/s (JESD204A) or 12Gb/s (JESD204B)
speeds. Transferring data at these speeds requires an FPGA with
high-speed transceivers, which are usually on the more expensive end
of the spectrum (especially if you want to run at 12Gb/s). The other
thing to beware of is that the higher-end FPGAs usually aren't
supported by the free version of the tools. Altera/Intel Cyclone V
GX and SX families have transceivers that run up to 3.125Gb/s, while
the Cyclone V GT and ST variants have transceivers that run up to
6.144Gb/s. All Cyclone V parts are covered by the free tools. The
"S" versions in the series (SX and ST) are SoC parts that contain
on-board ARM CPUs (either single or dual core). <br>
<br>
So we get boxed in by the required FPGA performance and the (usually
large) cost of the full version of the tools. It would be great if
you can find an ADC that is both affordable and that we can
interface to a reasonably priced FPGA. There are some amazing parts
made today, but it is a hard selection process with so many
variables to consider.<br>
<br>
73,<br>
Scotty WA2DFI<br>
<br>
<div class="moz-cite-prefix">On 2019-02-02 14:51, David Vieira
wrote:<br>
</div>
<blockquote type="cite"
cite="mid:700059557.2014457.1549144267487@mail.yahoo.com">
<meta http-equiv="content-type" content="text/html; charset=UTF-8">
<div class="ydp41005f1dyahoo-style-wrap"
style="font-family:Helvetica Neue, Helvetica, Arial,
sans-serif;font-size:13px;">
<div>Scott - </div>
<div>I like the idea of a single Mixer and no phase shifter to
create I/Q in the RF/analog world.</div>
<div>That would help a lot with discrete, high performance
designs.</div>
<div><br>
</div>
<div>As for the core question - what is the rate from ADC to
FPGA --- that seems both flexible yet with out a clear cut
answer.</div>
<div>Lots of good discussion to box in the trade-offs, though.</div>
<div><br>
</div>
<div>I'll try and look at discrete ADC options that could handle
the range of 144 or even 900 MHz, with at least nyquist
sampling.</div>
<div><br>
</div>
<div>regards,</div>
<div><br>
</div>
<div>David, KI6CLA</div>
<div><a class="moz-txt-link-abbreviated" href="mailto:dpv@ieee.org">dpv@ieee.org</a> </div>
<div><br>
</div>
<div><br>
</div>
</div>
<div id="ydpd534381fyahoo_quoted_9961111753"
class="ydpd534381fyahoo_quoted">
<div style="font-family:'Helvetica Neue', Helvetica, Arial,
sans-serif;font-size:13px;color:#26282a;">
<div> On Saturday, February 2, 2019, 1:13:15 PM PST, Scotty
Cowling via Ground-Station
<a class="moz-txt-link-rfc2396E" href="mailto:ground-station@lists.openresearch.institute"><ground-station@lists.openresearch.institute></a> wrote: </div>
<div><br>
</div>
<div><br>
</div>
<div>
<div dir="ltr">This is a great discussion, sorry I have
arrived so late in the thread.<br>
</div>
<div dir="ltr"><br>
</div>
<div dir="ltr">Since I am a FPGA and a hardware guy, my
comments are hardware-centric. <br>
</div>
<div dir="ltr">Probably makes me odd man out, but here
goes...<br>
</div>
<div dir="ltr"><br>
</div>
<div dir="ltr">I greatly favor a single ADC at a higher rate
(than dual ADCs clocked in <br>
</div>
<div dir="ltr">phase or quadrature). The I and Q samples can
be generated <br>
</div>
<div dir="ltr">mathematically inside the FPGA without the
analog mismatch problems <br>
</div>
<div dir="ltr">associated with trying to build two identical
copies of analog and ADC <br>
</div>
<div dir="ltr">hardware. The quadrature mixers are
implemented in digital hardware to <br>
</div>
<div dir="ltr">whatever precision the hardware allows. Of
course, there is a price to <br>
</div>
<div dir="ltr">be paid. The ADC has to run twice as fast,
and wider NCOs and <br>
</div>
<div dir="ltr">multipliers use FPGA fabric and require
fasted logic. Both cost $$<br>
</div>
<div dir="ltr"><br>
</div>
<div dir="ltr">While the AD9361 is a fantastic part, we pay
for all the features <br>
</div>
<div dir="ltr">whether we use them or not. Mixers and
oscillators all add noise, <br>
</div>
<div dir="ltr">whether they are all integrated inside one
chip or spread out. System <br>
</div>
<div dir="ltr">engineering is in order.<br>
</div>
<div dir="ltr"><br>
</div>
<div dir="ltr">As Zach said, every decimation by 4 increases
dynamic range by <br>
</div>
<div dir="ltr">approximately 1 bit. So we should sample as
fast as possible, and <br>
</div>
<div dir="ltr">decimate in the digital domain. Except that
ADC width and speed cost <br>
</div>
<div dir="ltr">money, and the FGPA's ability to consume and
process data is limited in <br>
</div>
<div dir="ltr">speed. So we want to pick ADC width, clock
speed and FPGA based on the <br>
</div>
<div dir="ltr">knee of the price-performance curve. This
"knee" is always moving, which <br>
</div>
<div dir="ltr">is why today's hardware is better than
yesterday's (well, usually).<br>
</div>
<div dir="ltr"><br>
</div>
<div dir="ltr">My guess is that the practical, affordable
ADC performance today is at <br>
</div>
<div dir="ltr">~125Msps and either 14 or 16 bits.
Interestingly, affordable FPGAs can <br>
</div>
<div dir="ltr">handle 150MHZ to 200MHz at their inputs and
outputs without too much <br>
</div>
<div dir="ltr">problem. Go much faster, and you get really
expensive really fast. The <br>
</div>
<div dir="ltr">same with resources. I am most familiar with
Altera/Intel FPGAs, so <br>
</div>
<div dir="ltr">someone with Xilinx experience can add to
this. The best cost per logic <br>
</div>
<div dir="ltr">element seems to be either the MAX10M50 (50K
LEs) or the Cyclone 5 E <br>
</div>
<div dir="ltr">(logic only series). The C5E goes up to 300K
LEs (which is a lot, and <br>
</div>
<div dir="ltr">costs appropriately). If we want a dual-core
ARM hard processor <br>
</div>
<div dir="ltr">(per-configured in silicon, using zero LEs),
the Cyclone 5 SE at 110K <br>
</div>
<div dir="ltr">LEs is probably the best bet.<br>
</div>
<div dir="ltr"><br>
</div>
<div dir="ltr">So where does this leave us for P4G hardware?
Some kind of down <br>
</div>
<div dir="ltr">conversion at the antenna is pretty obvious.
Is it better to use an off <br>
</div>
<div dir="ltr">the shelf LNB to a higher frequency (e.g.,
900MHz) and then down-convert <br>
</div>
<div dir="ltr">to base band at the SDR receiver front end?
Or is it better to use a <br>
</div>
<div dir="ltr">custom LNB and down convert directly to a
base band frequency (say <br>
</div>
<div dir="ltr">30MHz) that can be directly sampled?<br>
</div>
<div dir="ltr"><br>
</div>
<div dir="ltr">A third option would be to build a VHF or UHF
direct-sampling SDR (at <br>
</div>
<div dir="ltr">900MHz, to use the above example), but I
think that would be too expensive.<br>
</div>
<div dir="ltr"><br>
</div>
<div dir="ltr">73,<br>
</div>
<div dir="ltr">Scotty WA2DFI<br>
</div>
<div dir="ltr"><br>
</div>
<div dir="ltr"><br>
</div>
<div dir="ltr"><br>
</div>
<div dir="ltr">_______________________________________________<br>
</div>
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