[Ground-station] RISC-V on SOI

[Bruce Perens]

And this is an IP core for a particular foundary's SOI process, not an
independent device.

On Wed, Jul 11, 2018 at 11:07 AM, Bruce Perens <bruce at perens.com> wrote:

> REM has the Open Source RISC-V CPU architecture, apparently their own
> proprietary version, in silicon-on-insulator. They are vending it as
> radically low power with robust timing independent of clock frequency, not
> as a rad-hard device. http://remicro.com/risc-v-ip
>
> --
> Bruce Perens K6BP - CEO, Legal Engineering
> Standards committee chair, license review committee member, co-founder,
> Open Source Initiative
> President, Open Research Institute; Board Member, Fashion Freedom
> Initiative.
>



-- 
Bruce Perens K6BP - CEO, Legal Engineering
Standards committee chair, license review committee member, co-founder,
Open Source Initiative
President, Open Research Institute; Board Member, Fashion Freedom
Initiative.
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