[Ground-station] Theseus Cores polyphase channelizer - build progress - home stretch? Errors!

[Michelle Thompson]

Working on getting the polyphase channelizer from Theseus Cores up and
running in RFNoC. This is critical for payload and Groundsat.

Plenty of things to figure out along the way. I've been keeping track of
all the steps in a set of notes. Those notes are attached.

Here is the current sticking point. Today I attempted to build the
dsp-utils example with uhd_image_builder.

This is a set of blocks in parallel to the channelizer. It's the example
that comes with the repository, so seemed like a good thing to try and do.

However, the dsp-utils build example failed. Error message below.

What am I doing wrong? Any ideas for when I start back up tomorrow on this?

Looking forward, it looks like there's at least one to-do for the
channelizer:
"TODO: implement generate options to reduce/increase resource usage based
on desired channelizer size" I'm sure there's plenty more to do.

When we get up to speed on the logistics of getting blocks in and out of
the prototyping hardware, then we can start putting it on the air and
contributing improvements.

More soon!
-mdt


[00:18:58] Executing Tcl: opt_design -directive NoBramPowerOpt
[00:18:58] Starting Logic Optimization Command
[00:18:58] Current task: Logic Optimization +++ Current Phase: Starting
[00:18:58] Current task: Logic Optimization +++ Current Phase: Finished
[00:18:58] Starting DRC Task
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net bus_clk_gen/inst/CLK_OUT4 has
multiple drivers: radio_clk_gen/inst/clkout1_buf/O, and
bus_clk_gen/inst/clkout4_buf/O.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net
radio_reset_sync/reset_double_sync/synchronizer_false_path/value[9]_9 has
multiple drivers:
ce_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q,
and
radio_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.
[00:19:04] Current task: DRC +++ Current Phase: Starting
[00:19:04] Current task: DRC +++ Current Phase: Finished
[00:19:04] Process terminated. Status: Failure

========================================================
Warnings:           1352
Critical Warnings:  39
Errors:             4

Makefile.x300.inc:106: recipe for target 'bin' failed
make[1]: *** [bin] Error 1
make[1]: Leaving directory
'/home/abraxas3d/rfnoc/src/uhd-fpga/usrp3/top/x300'
Makefile:112: recipe for target 'X310_RFNOC_HG' failed
make: *** [X310_RFNOC_HG] Error 2
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